About the Program

Objectives of the Program
  • To provide an in-depth understanding of the effectiveness and practical benefits of using open-source Verilog simulators for simulating, debugging, and optimizing digital circuits.
  • To demonstrate the integration of open-source Verilog simulators in the digital design workflow, from coding to visualization of simulation results.
Expected Outcome of the Program
  • Participants will gain the skills to use online simulation tools to implement Verilog code for designing a variety of digital circuits.
  • Participants will be introduced to industry-standard simulation tools and their practical applications.

Important Dates

Date 18th - 19th Dec 2024
Time 09:30 AM to 05:00 PM
Target Audience All 3 rd semester CS&E students
Type of program Offline
Venue AI-06-2F-07-LR & AI-06-2F-08-LR

Resource Person Details

Committee Members

  • Dr. Rajeshwari, Principal, AIT
  • Prof. Marigowda C K, Vice-Principal, AIT
  • Mr. Rajeev Bilagi, Assistant Professor and in-charge HOD, Dept. of CS&E